R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 483

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.2
Table 12.1 shows the DDRIF pin configuration. For details on connection with the DDR-SDRAM,
see the LSI pin information section. Note that clock-related signals will be determined later.
Table 12.1 Pin Configuration
Pin Name
M_CLK0
M_CLK1
M_CKE
M_CS
M_WE
M_A13 to M_A0
M_BA1, M_BA0
M_D31 to M_D0
M_DQS3 to M_DQS0 I/O data strobe
M_DQM3 to M-DQM0 Data mask
M_RAS
M_CAS
M_BKPRST
M_VREF
Input/Output Pins
Function
DDR-SDRAM clock
DDR-SDRAM clock
Clock enable
Chip select
Write enable
Address
Bank active
Data
Row address strobe
Column address strobe
Power back-up reset
Reference voltage input
I/O
Output
Output
Output
Output
Output
Output
Output
I/O
I/O
Output
Output
Output
Input
Input
Section 12 DDR-SDRAM Interface (DDRIF)
Rev. 2.00 May 22, 2009 Page 413 of 1982
Description
Clock output for DDR-SDRAM
Clock output for DDR-SDRAM
Inverted clock output of M_CLK0
When this pin goes high, the clock
signal is active. When this pin goes
low, the clock signal is inactive.
Chip select output
Write enable output
Row/column address
Bank address output
Data I/O
I/O data strobe
I/O data mask signal
Row address strobe signal
Column address strobe signal
When this pin goes low, the M_CKE
pin shall go low
Input reference voltage
REJ09B0256-0200