R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1326

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 30 SIM Card Module (SIM)
Rev. 2.00 May 22, 2009 Page 1256 of 1982
REJ09B0256-0200
Bit
5
4
Bit Name
ORER
ERS
Initial
Value
0
0
R/W
R/W
R/W
Description
Overrun Error
Indicates that an overrun error occurred during reception,
resulting in abnormal termination.
0: Indicates that reception is in progress, or that reception
[Clearing conditions]
•
•
1: Indicates that an overrun error occurred during
[Setting condition]
When the RDRF bit is set to 1 and the next serial reception
is completed.
Notes:
Error Signal Status
Indicates the status of error signals returned from the
receive side during transmission. In T = 1 mode, this flag is
not set.
0: Indicates that an error signal indicating detection of a
[Clearing conditions]
•
•
1: Indicates that an error signal indicating detection of a
[Setting condition]
When an error signal is sampled.
Note:
parity error was not sent from the receive side
parity error was sent from the receive side
was completed normally*
reception*
On reset
When 0 is written to the ORER bit
On reset
When 0 is written to the ERS bit
Even if the TE bit in SCSCR is cleared to 0, the
ERS flag is unaffected, and the previous state is
retained.
1. When the RE bit in SCSCR is cleared to 0, the
2. In SCRDR, the received data before the
ORER flag is unaffected and the previous state
is retained.
overrun error occurred is lost, and the data that
had been received at the time when the
overrun error occurred is retained. Further, with
the ORER bit set to 1, subsequent serial
reception cannot be continued.
2
1