R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1012

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
frame (single-frame/multi-buffer). As an example of single-frame/multi-buffer operation, the data
portion that is used in a fixed manner in each Ethernet frame transmission can be referenced by
multiple descriptors. For example, multiple descriptors can share the destination address and
transmit source address in an Ethernet frame, and the remaining data can be stored in each
separate buffer.
(a)
Before the TR bits in EDTRR are set to 11, the user sets whether the bits of the descriptor are
valid or invalid bit and sets other descriptor configuration. After Ethernet frame transmission, the
E-DMAC disables the valid/invalid bits of the descriptor and writes status information. This
operation is referred to as write-back.
When using TD0, the user should write desired values to bits 31 to 28 and 26 according to the
descriptor configuration. Bits 27 and 25 to 0 should be cleared to 0.
Rev. 2.00 May 22, 2009 Page 942 of 1982
REJ09B0256-0200
Note: *According to the descripotr lenght set by the DL0 and DL 1 bits in EDMR, the padding size is detemined as follows:
Transmit Descriptor 0 (TD0)
For 16 bytes Padding = 4 bytes
For 32 bytes padding = 20bytes
For 64 bytes Padding = 52bytes
TD0
TD1
TD2
Figure 23.3 Relationship between Transmit Descriptor and Transmit Buffer
Transmit deschriptor
31
A
C
T
T
31
31
30
D
T
L
E
29 28
T
F
P
27
T
F
E
TDL
26
E
T
F
I
Padding (4/20/52 bytes)*
25
Reserved
16
TBA
12 11
TFS[26:0]
0
0
Transmit buffer
Valid transmit data