R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 340

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Interrupt Controller (INTC)
Rev. 2.00 May 22, 2009 Page 270 of 1982
REJ09B0256-0200
Bit
31 to 26 —
25
24
23, 22
21
20
19, 18
17
16
15
14
13
12
11
10
Bit Name
SCIF2
USBF
STIF1
STIF0
USBH
GETHER
PCC
ADC
TPU
SIM
Initial
Value
All 0
0
0
All 0
0
0
All 0
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
This bit is always read as 0.
The write value should
always be 0.
Indicates SCIF2 interrupt
source
Indicates USBF interrupt
source
These bits are always read
as 0. The write value should
always be 0.
Indicates STIF1 interrupt
source
Indicates STIF0 interrupt
source
Undefined values are read
from these bits. The write
value should always be 0
Indicates USBH interrupt
source
Indicates GETHER interrupt
source
Indicates PCC interrupt
source
This bit is always read as 0.
The write value should
always be 0.
Undefined value is read
from this bit.
The write value should
always be 0.
Indicates ADC interrupt
source
Indicates TPU interrupt
source
Indicates SIM interrupt
source
Description
Indicates interrupt
sources for each
peripheral module
(INT2A01 is not affected
by the state of the
interrupt mask register).
0: No interrupts
1: Interrupts are
Note: Reading the
generated
INTEVT code
notified to the CPU
directly can identify
interrupt sources.
In this case,
reading INT2A01 is
not necessary.

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