R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1694

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 37 LCD Controller (LCDC)
37.3.22 LCDC Memory Access Interval Number Register (LDLIRNR)
LDLIRNR controls the bus cycle interval when the LCDC reads VRAM. When LDLIRNR is set
to a value other than H'00, the LCDC does not access VRAM until clock count of the DDR-
SDRAM matches the value set in LDLIRNR. When LDLIRNR is set to H'00 (initial value), the
LCDC accesses VRAM one clock after the LCDC accessed VRAM.
Rev. 2.00 May 22, 2009 Page 1624 of 1982
REJ09B0256-0200
Initial value:
Bit
15 to 8 
7 to 0
R/W:
Bit:
Bit Name
LIRN[7:0]
15

R
0
14

R
0
13

R
0
Initial Value
All 0
All 0
12

R
0
11

R
0
10

R
0
R/W
R
R/W

R
9
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
VRAM Read Bus Cycle Interval
Specifies the number of the DDR-SDRAM clock
cycles which can be performed during burst cycles
to read VRAM by LCDC.
H'00: one clock cycle
H'01: one clock cycle
H'02: two clock cycles
H'FE: 254 clock cycles
H'FF: 255 clock cycles

R
8
0
R/W
7
0
:
R/W
0
6
R/W
5
0
R/W
4
0
LIRN[7:0]
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0