R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 827

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
21.3
21.3.1
The CMT starts the operation of the counter by writing a 1 to the STRn bit in CMSTR of a
channel that has been selected for operation. Complete all of the settings before starting the
operation. Do not change the register settings other than by clearing flag bits.
The counter operates in one of two ways.
• One-Shot Operation
• Free-Running Operation
One-shot operation is selected by setting the CMM bit in CMCSR to 0. When the value in
CMCNT matches the value in CMCOR, the value in CMCNT is cleared to H'00000000 and
the CMF bit in CMCSR is set to 1. Counting by CMCNT stops after it has been cleared.
To detect an overflow interrupt, set the value in CMCOR to H'FFFFFFFF. When the value in
CMCNT matches the value in CMCOR, CMCNT is cleared to H'00000000 and bits CMF and
OVF in CMCSR are set to 1.
Free-running operation is selected by setting the CMM bit in CMCSR to 1. When the value in
CMCNT matches the value in CMCOR, CMCNT is cleared to H'00000000 and the CMF bit in
CMCSR is set to 1. CMCNT resumes counting-up after it has been cleared.
To detect an overflow interrupt, set CMCOR to H'FFFFFFFF. When the values in CMCNT
and CMCOR match, CMCNT is cleared to H'00000000 and bits CMF and OVF in CMCSR
are set to 1.
H'00000000
CMCOR
Value in
CMCNT
Operation
Counter Operation
Figure 21.2 Counter Operation (One-Shot Operation)
CMF = 1
OVF = 1 (When an overflow is detected)
Rev. 2.00 May 22, 2009 Page 757 of 1982
Section 21 Compare Match Timer (CMT)
REJ09B0256-0200
Time

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