R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1627

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

36.3.39 Timer Register (TMRH/TMRL)
TMRH/TMRL is a 16-bit timer which is operated with a peripheral clock φ. Measuring the SOF
packet reception interval enables the SOF packet break to be detected.
The timer is operated, stopped, and cleared according to the settings of the control register 1
(CTLR 1)
TMRH/TMRL is handled as a 16-bit (TMR[15:0]) register in the USBF which consists of
TMR[15:8] bits in TMRH and TMR[7:0] bits in TMRL. Although TMRH can be read directly,
TMRL is read via an 8-bit temporary register. Therefore, the registers should be read in the order
of TMRH and TMRL in byte units. TMRL cannot be read singly.
• TMRH
Bit
31 to 8
7 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit: 31
Bit: 15
Bit Name

TMR[15:8]
R/W
—
—
R
0
R/W
30
—
14
—
R
0
R/W
29
—
13
—
R
0
Initial value R/W Description
Undefined
0
R/W
28
12
—
—
R
0
R/W
27
11
—
—
R
0
R/W
26
10
—
—
R
0
R
R/W Upper Eight Bits of Count Value
R/W
25
—
—
R
9
0
Reserved
These bits are always read as undefined value. The
write value should always be 0.
R/W
TMR[15:8]
24
—
—
R
8
0
R/W
23
—
—
R
7
0
Section 36 USB Function Controller (USBF)
Rev. 2.00 May 22, 2009 Page 1557 of 1982
R/W
22
—
—
R
6
0
R/W
21
—
—
R
5
0
R/W
20
—
—
R
4
0
R/W
19
—
—
R
3
0
REJ09B0256-0200
R/W
18
—
—
R
2
0
R/W
17
—
—
R
1
0
R/W
16
—
—
R
0
0