R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 679

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(SAR, DAR, TCR, CHCR, DMAOR,
TCR – 1 → TCR, SAR, and DAR updated
SARB, DARB, TCRB, DMARS)
Reload mode: TCR[7:0] → TCRBL
Notes: 1. In repeat mode, a transfer request is acceptted with TE =1 when HIE = 1 and HE = 0
Transfer request occurs?
Transfer (1 transfer unit);
DEI interrupt request
NMIF = 1 or AE =1 or
DE = 0 or DME = 0?
TE, AE, NMIF = 0?
DE, DME = 1 and
Reload mode?
Repeat mode?
Initial settings
Normal end
Yes
Yes
2. In auto-request mode, transfer starts when bits NMIF, AE, and TE are all 0 or bits TE
3. DREQ is level detection (external requesrt) in burst mode or cycle-steral mode.
4. DREQ is edge detection (external request) or auto request in burst mode.
5. Loading to SAR and DAR differs according to the operating conditions in each mode.
TCR = 0?
Yes
No
No
No
(IE = 1)
TE = 1
Start
(half end interrupt is enable and clear the HE to 0 after HE is set to 1).
and HIE are 1 and HE is 0 (in repeat mode), and bits DE and DME are set to 1.
*
*
1
2
Figure 14.11 DMA Transfer Flowchart
Yes
No
Yes
No
Yes
No
No
TCR[23:16] → TCR[7:0] load
*
6
SARB/DARB load
TCRB → TCR load
HIE = 0 or HE = 1?
SARB/DARB load
TCR[7:0] = 0?
Yes
Yes
Section 14 Direct Memory Access Controller (DMAC)
*
*
No
*
5
6
5
No
HE = 1, DEI interrupt
NMIF = 1 or AE = 1 or
request (HIE = 1)
TCR = TCRB/2?
DE = 0 or DME = 0?
Transfer end
Rev. 2.00 May 22, 2009 Page 609 of 1982
Yes
Yes
*
4
transfer request mode
Bus mode, DREQ
detection system,
No
*
REJ09B0256-0200
3

Related parts for R5S77631Y266BGV