R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1874

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 42 User Debugging Interface (H-UDI)
42.4
The H-UDI has the following registers.
Table 42.3 Register Configuration (1)
Notes: 1. The area P4 address is an address when accessing through area P4 in a virtual
Table 42.4 Register Configuration (2)
Note:
Table 42.5 Register Status in Each Processing State
Rev. 2.00 May 22, 2009 Page 1804 of 1982
REJ09B0256-0200
Register Name
Instruction register
Interrupt source register
Boundary scan register
Bypass register
Register Name
Instruction register
Interrupt source register
Boundary scan register
Bypass register
Register Name
Instruction register
Interrupt source register SDINT
2. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller
1. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller
2. When reading via the H-UDI, the value is always H'FFFF FFFD.
3. Only 1 can be written to the LSB by the H-UDI interrupt command.
Register Descriptions
address space. The area 7 address is an address when accessing through area 7 in a
physical space using the TLB.
initializes to these values.
initializes to these values.
Abbrev.
SDIR
Abbrev.
SDIR
SDINT
SDBSR
SDBPR
Abbrev.
SDIR
SDINT
SDBSR
SDBPR
R/W
R
R/W


R/W
R/W
W*

R/W
Power-On Reset
H'0EFF
H'0000
3
Area P4
Address*
H'FC11 0000
H'FC11 0018


Size
32
32

1
1
Manual Reset Sleep
Retained
Retained
H-UDI Side
Undefined
Area 7 Address*
H'1C11 0000
H'1C11 0018


Initial Value*
H'FFFF FFFD (fixed value*
H'0000 0000

CPU Side
Retained
Retained
1
1
Size
16
16


Standby
Retained
Retained
Initial
Value*
H'0EFF
H'0000


2
)
2