R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 319

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Note: When the IRQ is set as level input (IRQnS1 = 1), an interrupt source is held until the CPU
9.3.3
INTPRI is a 32-bit readable/writable register that sets the IRQ[7:0] interrupt priorities (levels 15 to
0). This setting is valid only when using IRQ7/IRL7 to IRQ4/IRL4 and IRQ3/IRL3 to IRQ0/IRL0
as IRQ independent interrupts input to set the IRLM0 and IRLM1 bits to 1 in ICR0.
Initial value:
Initial value:
Bit
31, 30
29, 28
27, 26
25, 24
23, 22
21, 20
19, 18
17, 16
15 to 0
R/W:
R/W:
Bit:
Bit:
accepts an interrupt (not always IRQ). Therefore even if an interrupt source is disabled
before this LSI returns from sleep mode, it is guaranteed that processing is branched to the
interrupt handler when this LSI returns from sleep mode. The held interrupt can be cleared
by setting the corresponding interrupt mask bit (the IM bit in the interrupt mask register) to
1.
Interrupt Priority Register (INTPRI)
Bit Name

IRQ0S
IRQ1S
IRQ2S
IRQ3S
IRQ4S
IRQ5S
IRQ6S
IRQ7S
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
IP0
IP4
Initial
Value
0
0
0
0
0
0
0
0
All 0
R/W
R/W
29
13
0
0
R/W
R/W
28
12
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
27
11
0
0
R/W
R/W
26
10
0
0
IP1
IP5
Description
IRQn Sense Select (n = 0 to 7)
Selects whether interrupt signals to the IRQ7/IRL7 to
IRQ0/IRL0 pins are detected at the rising edge, falling
edge, high level, or low level.
00: Interrupt requests are detected at the falling edge
01: Interrupt requests are detected at the rising edge
10: Interrupt requests are detected at the low level of
11: Interrupt requests are detected at the high level of
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
R/W
25
0
9
0
IRQn input
IRQn input
of IRQn input
of IRQn input
R/W
R/W
24
0
8
0
R/W
R/W
23
0
7
0
Rev. 2.00 May 22, 2009 Page 249 of 1982
R/W
R/W
22
0
6
0
IP2
IP6
Section 9 Interrupt Controller (INTC)
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
REJ09B0256-0200
R/W
R/W
18
0
2
0
IP3
IP7
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0