R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1242

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(5)
Figures 28.16 and 28.17 show a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
When switching the operating mode from asynchronous mode to clocked synchronous mode
without initializing the SCIF, make sure that the ORER flag is cleared to 0.
Rev. 2.00 May 22, 2009 Page 1172 of 1982
REJ09B0256-0200
Serial Data Reception (Clocked Synchronous Mode)
No
No
Read ORER flag in SCLSR
Clear RE bit in SCSCR to 0
Read RDF flag in SCFSR
SCFRDR, and clear RDF
Read receive data in
flag in SCFSR to 0
All data received?
Start of reception
End of reception
Initialization
ORER = 1?
RDF = 1?
Figure 28.16 Sample Serial Reception Flowchart (1)
No
Yes
Yes
Error handling
[1]
[3]
[4]
Yes
[2]
[1] SCIF initialization:
[2] Receive error handling:
[3] SCIF status check and receive data read:
[4] Serial reception continuation procedure:
See Sample SCIF Initialization Flowchart in figure
28.13.
Read the ORER flag in SCLSR to identify any error,
perform the appropriate error handling, then clear
the ORER flag to 0.
Transmission/reception cannot be resumed while the
ORER flag is set to 1.
Read SCFSR and check that RDF = 1, then read the
receive data in SCFRDR, and clear the RDF flag to
0. The transition of the RDF flag from 0 to 1 can also
be identified by an RXI interrupt.
To continue serial reception, read at least the receive
trigger set number of receive data bytes from SCFRDR,
read 1 from the RDF flag, then clear the RDF flag to 0.
The number of receive data bytes in SCFRDR can
be ascertained by reading SCFDR.
However, as starting up the DMAC using RXI and
reading the value of SCFDR automatically clears bit
RDF, clearing bit RDF is not required.