R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 560

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 PCI Controller (PCIC)
(2)
Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Rev. 2.00 May 22, 2009 Page 490 of 1982
REJ09B0256-0200
Initial value:
Initial value:
Bit
1
0
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
PCI Local Space Register 0 (PCILSR0)
Bit:
Bit:
Bit Name
RSTCTL
CFINIT
31
15
—
—
R
R
R
R
0
0
30
14
—
—
R
R
R
R
0
0
Initial
Value
0
0
29
13
—
—
R
R
R
R
0
0
R/W
28
12
—
R
R
R
0
0
R/W
SH: R/W
PCI: R
SH: R/W
PCI: R
R/W
27
11
—
R
R
R
0
0
R/W
26
10
—
R
R
R
0
0
Description
PCIRESET Output
Controls the PCIRESET output by software. This bit is
valid when the PCIC operates in host bus bridge
mode.
0: Negates PCIRESET output (high level output)
1: Asserts PCIRESET output (low level output)
Note: The PCIRESET is also asserted during power-
PCI Internal Register Initialize Control
Set this bit to 1 after the initialization of the PCIC
internal registers are completed. Setting this bit
enables accesses from the PCI bus. During
initialization in host bus bridge mode, the bus is not
given to the device on the PCI bus. In normal mode,
the PCIC returns RETRY when it is accessed from the
PCI bus.
0: During initialization
1: Initialization completed
R/W
25
—
R
R
R
0
9
0
LSR
R/W
on reset.
24
—
R
R
R
0
8
0
R/W
23
—
R
R
R
0
7
0
R/W
22
—
R
R
R
0
6
0
R/W
21
—
R
R
R
0
5
0
R/W
20
—
R
R
R
0
4
0
19
—
—
R
R
R
R
0
3
0
18
—
—
R
R
R
R
0
2
0
17
—
—
R
R
R
R
0
1
0
R/W
MBA
16
RE
—
R
R
R
0
0
0