R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 444

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 11 Local Bus State Controller (LBSC)
11.5.4
Burst ROM Interface
Setting the TYPE bit in CSnBCR(n=0 to 2 and 4 to 6) to 010 allows a burst ROM to be connected
to areas 0 to 2 and 4 to 6. The burst ROM interface provides high-speed access to ROM that has a
burst access function. The burst access timing of burst ROM is shown in figure 11.12. The wait
cycle is set to 0 cycle. Although the access is similar to that of the SRAM interface, only the
address is changed when the first cycle ends and then the next access is started. When 8-bit ROM
is used, the number of consecutive accesses can be set as 4, 8, 16, or 32 through bits BST[2:0] in
CSnBCR(n=0 to 2 and 4 to 6). Similarly, when 16-bit ROM is used, 4, 8 or 16 accesses can be set;
when 32-bit ROM is used, 4 or 8 accesses can be set.
The RDY signal is always sampled when one or more wait cycles are set. Even when no wait is
specified in the burst ROM settings, two access cycles are inserted in the second and subsequent
accesses as shown in figure 11.13.
A writing operation for the burst ROM interface is performed in the same way as for the SRAM
interface.
In a 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus
width. The first access is performed on the data for which there was an access request, and the
remaining accesses are performed in wrap around method according to the set bus width. The bus
is not released during this transfer.
Figure 11.14 shows the timing chart when the burst ROM is used and setup/hold is specified by
CSnWCR.
Rev. 2.00 May 22, 2009 Page 374 of 1982
REJ09B0256-0200