R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1505

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
26
25
Bit Name
OIRQ
IIRQ
Initial
Value
0
0
*
2
R/W
R/W
R
*
1
Description
Overflow Error Interrupt Status Flag
This status flag indicates that the data has been
supplied at a higher rate than the required rate.
This bit is set to 1 regardless of the setting of OIEN bit.
In order to clear it to 0, write 0 in it.
If OIRQ = 1 and OIEN = 1, then an interrupt will be
generated.
When TRMD = 0 (Receive Mode):
If OIRQ = 1, it indicates that the previous unread data
had not been read out before new unread data was
written in SSIRDR. This may cause the loss of data,
which can lead to destruction of multi-channel data.
Note: When overflow error occurs, the data in the data
When TRMD = 1 (Transmit Mode):
If OIRQ = 1, it indicates that SSITDR had data written in
before the data in SSITDR was transferred to the shift
register. This may cause the loss of data, which can
lead to destruction of multi-channel data.
Idle Mode Interrupt Status Flag
This status flag indicates whether the SSI module is in
the idle status. This bit is set to 1 regardless of the
setting of IIEN bit, so that polling will be possible.
The interrupt can be masked by clearing IIEN bit to 0,
but writing 0 in this bit will not clear the interrupt.
If IIRQ = 1 and IIEN = 1, then an interrupt will be
generated.
0: The SSI module is not in the idle status.
1: The SSI module is in the idle status.
buffer will be overwritten by the next data sent
from the SSI interface.
Rev. 2.00 May 22, 2009 Page 1435 of 1982
Section 34 Serial Sound Interface (SSI)
REJ09B0256-0200

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