R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 499

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.4.5
SDMR is used to set the DDR-SDRAM mode register and extended mode register. Since SDMR
is not physically contained in the DDRIF, reading this register is invalid. Only write addresses
have a meaning for the DDR-SDRAM and the write data is ignored.
When SDMR is written to, signals are output to pins connected to the DDR-SDRAM according to
the table shown below.
Address bits 12 to 3 correspond to external pins M_A9 to M_A0, address bits 14 and 13 to
external pins M_BA1 and M_BA0, and address bits 18 to 15 to external pins M_A13 to M_A10.
Bit
63 to 12 
11 to 8
7 to 0
n-1
H
M_CKE
DDR-SDRAM Mode Register (SDMR)
Bit Name

SPLIT
n
H
M_CS
L
Initial
Value
All 0
0001
All 0
M_RAS
L
R/W
R
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DDR-SDRAM Memory Configuration
These bits specify the DDR-SDRAM row/column
configuration.
0001: 12 × 9 (= 8 M × 16 bits product)
0011: 13 × 9 (= 16 M × 16 bits product)
0100: 13 × 10 (= 32 M × 16 bits product)
0110: 14 × 10 (= 64 M × 16 bits product)
Other than above: Setting prohibited
The relationship between the SPLIT bits and
row/column is shown in section 12.5.12, Address
Multiplexing.
Reserved
These bits are always read as 0. The write value should
always be 0.
M_CAS
L
M_WE
L
Section 12 DDR-SDRAM Interface (DDRIF)
Rev. 2.00 May 22, 2009 Page 429 of 1982
M_BA1 and
M_BA0
Bits 14 and
13
Address Bit Correspondence
M_A13 to
M_A10
Bits 18 to
15
REJ09B0256-0200
M_A9 to
M_A0
Bits 12 to
3