R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1558

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 35 USB Host Controller (USBH)
35.3.22 HcRhPortStatus[2] Register (USBHRPS2)
This register is reset by the UsbReset state.
Rev. 2.00 May 22, 2009 Page 1488 of 1982
REJ09B0256-0200
Initial value :
Initial value :
Bit
31 to 21
20
19
18
17
R/W :
R/W :
Bit :
Bit :
Bit Name
PRSC
OCIC
PSSC
PESC
31
15
R
R
0
0
30
14
R
R
0
0
29
13
Initial value
All 0
0
0
0
0
R
R
0
0
28
12
R
R
0
0
27
11
R
R
0
0
R/W Description
R
R/W PortResetStatusChange
R/W PortOverCurrentIndicatorChange
R/W PortSuspendStatusChange
R/W PortEnableStatusChange
26
10
R
R
0
0
LSDA PPS
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
This bit indicates that the port reset signal has
completed.
0: Port reset is not complete.
1: Port reset is complete.
This bit is set when OverCurrentIndicator changes.
Writing 1 clears this bit. Writing 0 has no effect.
This bit indicates the completion of the selective
resume sequence for the port.
0: Port is not resumed.
1: Port resume is complete.
This bit indicates that the port has been disabled due
to a hardware event (PortEnableStatus bit is cleared).
0: Port has not been disabled.
1: PortEnableStatus bit has been cleared.
25
R
0
9
R/W
24
R
0
8
0
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
PRSC OCIC PSSC PESC CSC
PRS POCI PSS
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
PES
17
0
1
0
R/W
CCS
R/W
16
0
0
0

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