R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1857

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

41.3.4
1. Table 41.4 shows the relation between the operand sizes specified using the match condition
Table 41.4 Relation between Operand Sizes and Address Bits to be Compared
2. When the data value is included in the channel 1 match conditions:
Selected Operand Size
Quadword
Longword
Word
Byte
Operand size is not included in the
match conditions
setting register (CBR0 or CBR1) and the address bits to be compared for the operand access
cycle break.
The above table means that if address H'00001003 is set in the match address setting register
(CAR0 or CAR1), for example, the match condition is satisfied for the following access cycles
(assuming that all the other conditions are satisfied):
 Longword access to address H'00001000
 Word access to address H'00001002
 Byte access to address H'00001003
If the data value is included in the match conditions, be sure to select the quadword, longword,
word, or byte as the operand size using the operand size select bit (SZ) of the match condition
setting register (CBR1), and also set the match data setting register (CDR1) and the match data
mask setting register (CDMR1). With these settings, the match condition is satisfied when
both of the address and data conditions are satisfied. The data value and mask control for byte
access, word access, and longword access should be set in bits 7 to 0, 15 to 0, and 31 to 0 in
the bits CDR1 and CDMR1, respectively. For quadword access, 64-bit data is divided into the
upper and lower 32-bit data units, and each unit is independently compared with the specified
condition. When either the upper or lower 32-bit data unit satisfies the match condition, the
match condition for the 64-bit data is determined to be satisfied.
Operand Access Cycle Break
Address Bits to be Compared
Address bits A31 to A3
Address bits A31 to A1
Address bits A31 to A0
Address bits A31 to A3 for quadword access
Address bits A31 to A2 for longword access
Address bits A31 to A1 for word access
Address bits A31 to A0 for byte access
Address bits A31 to A2
Rev. 2.00 May 22, 2009 Page 1787 of 1982
Section 41 User Break Controller (UBC)
REJ09B0256-0200