R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 25

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.4 Operation ........................................................................................................................... 938
23.5 Connection to PHY-LSI..................................................................................................... 986
23.6 Usage Notes ....................................................................................................................... 995
Section 24 IP Security Accelerator (SECURITY).............................................997
Section 25 Stream Interface (STIF) ...................................................................999
25.1 Features.............................................................................................................................. 999
25.2 Input/Output Pins ............................................................................................................. 1001
23.3.78 Transmit FIFO Threshold Register (TFTR).......................................................... 926
23.3.79 FIFO Depth Register (FDR) ................................................................................. 927
23.3.80 Receiving Method Control Register (RMCR) ...................................................... 928
23.3.81 Receive Descriptor Fetch Address Register (RDFAR)......................................... 929
23.3.82 Receive Descriptor Finished Address Register (RDFXR) .................................... 930
23.3.83 Receive Descriptor Final Flag Register (RDFFR) ................................................ 931
23.3.84 Transmit Descriptor Fetch Address Register (TDFAR) ....................................... 932
23.3.85 Transmit Descriptor Finished Address Register (TDFXR)................................... 933
23.3.86 Transmit Descriptor Final Flag Register (TDFFR)............................................... 934
23.3.87 Overflow Alert FIFO Threshold Register (FCFTR) ............................................. 935
23.3.88 Receive Data Padding Insert Register (RPADIR)................................................. 937
23.4.1 Descriptors and Descriptor List ............................................................................ 941
23.4.2 Transmission......................................................................................................... 958
23.4.3 Reception .............................................................................................................. 964
23.4.4 Relay ..................................................................................................................... 970
23.4.5 CAM Function ...................................................................................................... 971
23.4.6 Transmit/Receive Processing of Multi-Buffer Frame
23.4.7 Padding Insertion in Receive Data........................................................................ 975
23.4.8 Interrupt Processing .............................................................................................. 976
23.4.9 Activation Procedure ............................................................................................ 980
23.4.10 Flow Control......................................................................................................... 982
23.4.11 Magic Packet Detection ........................................................................................ 983
23.4.12 Direction for IEEE802.1Q Qtag............................................................................ 984
23.5.1 MII Frame Transmission/Reception Timing......................................................... 986
23.5.2 GMII/MII Frame Reception Timing ..................................................................... 988
23.5.3 RMII Frame Transmission/Reception Timing ...................................................... 990
23.5.4 Accessing MII Registers ....................................................................................... 991
23.5.5 MII-RMII Interface Conversion............................................................................ 993
23.6.1 Checksum Calculation of Ethernet Frames........................................................... 995
23.6.2 Notes on TSU Use ................................................................................................ 995
(Single-Frame/Multi-Descriptor) .......................................................................... 973
Rev. 2.00 May 22, 2009 Page xxiii of lxviii