R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 418

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 11 Local Bus State Controller (LBSC)
Rev. 2.00 May 22, 2009 Page 348 of 1982
REJ09B0256-0200
Bit
27
26 to 24 ADH
23
22 to 20 RDS
Bit Name


Initial
Value
0
111
0
111
R/W
R
R
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Address Hold Cycle
Specify the number of cycles to be inserted to ensure
the address hold time to the CSn negation. However,
setting to over one cycle, one cycle decremented from
the setting value when RD strobe cycle in read access
or WE strobe cycle in write access is set to over 1
cycle. (Available only when the SRAM interface, byte
control SRAM interface, or burst ROM interface is
selected.)
Note that, it will be no inserted cycle when setting to 0
for inserted wait cycle and setting to 0 for RD strobe
hold wait in read access or WE strobe hold wait in write
access.
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
RD Setup Cycle (CSn Assert–RD Assert Delay Cycle)
Specify the number of cycles to be inserted to ensure
the RD setup time to the T1. (Available only when the
SRAM interface, byte control SRAM interface, or burst
ROM interface is selected.)
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted