R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1215

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
5, 4
3
2
1
0
Bit Name
TTRG[1:0]
—
TFRST
RFRST
LOOP
Initial
Value
All 0
0
0
0
0
Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
R/W
R/W
R
R/W
R/W
R/W
Description
Transmit FIFO Data Number Trigger
These bits are used to set the number of remaining
transmit data bytes that sets the TDFE flag in SCFSR.
The TDFE flag is set when the number of transmit data
bytes in SCFTDR is equal to or less than the trigger set
number shown below.
00: 8 (8)
01:4 (12)
10: 2 (14)
11: 0 (16)
Note: * Figures in parentheses are the number of
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit FIFO Data Register Reset
Invalidates the transmit data in the transmit FIFO data
register and resets it to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * A reset operation is performed in the event of a
Receive FIFO Data Register Reset
Invalidates the receive data in the receive FIFO data
register and resets it to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * A reset operation is performed in the event of a
Loopback Test
Internally connects the transmit output pin (SCIF_TXD)
and receive input pin (SCIF_RXD) enabling loopback
testing.
0: Loopback test disabled
1: Loopback test enabled
empty bytes in SCFTDR when the flag is set.
power-on reset or manual reset.
power-on reset or manual reset.
*
Rev. 2.00 May 22, 2009 Page 1145 of 1982
REJ09B0256-0200