R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1508

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 34 Serial Sound Interface (SSI)
Note:
34.3.3
SSITDR is a 32-bit register that stores data to be transmitted.
Data written to SSITDR is transferred to the shift register as it is required for transmission. If the
data word length is less than 32 bits then its alignment should be as defined by the PDTA control
bit.
Reading this register will return the data in the buffer.
34.3.4
SSIRDR is a 32-bit register that stores the received data.
Data in SSIRDR is transferred from the shift register as each data word is received. If the data
word length is less than 32 bits then its alignment should be as defined by the PDTA control bit in
SSICR.
Rev. 2.00 May 22, 2009 Page 1438 of 1982
REJ09B0256-0200
Initial value:
Initial value:
Initial value:
Initial value:
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
1. These bits are readable/writable bits. If writing 0, these bits are initialized, although
2. At manual reset, the bit is undefined.
Transmit Data Register (SSITDR)
Receive Data Register (SSIRDR)
writing 1 is ignored.
R/W
R/W
31
15
31
15
R
R
0
0
0
0
R/W
R/W
30
14
30
14
0
0
0
0
R
R
R/W
R/W
29
13
29
13
R
R
0
0
0
0
R/W
R/W
28
12
28
12
R
R
0
0
0
0
R/W
R/W
27
11
27
11
R
R
0
0
0
0
R/W
R/W
26
10
26
10
0
0
0
R
0
R
R/W
R/W
25
25
0
0
0
0
R
R
9
9
R/W
R/W
24
24
R
R
0
8
0
0
8
0
R/W
R/W
23
23
R
R
0
7
0
0
7
0
R/W
R/W
22
22
R
R
0
6
0
0
6
0
R/W
R/W
21
21
0
0
0
R
0
R
5
5
R/W
R/W
20
20
R
R
4
4
0
0
0
0
R/W
R/W
19
19
3
3
0
0
0
R
0
R
R/W
R/W
18
18
2
2
0
0
0
R
0
R
R/W
R/W
17
17
R
R
1
1
0
0
0
0
R/W
R/W
16
16
0
0
0
0
0
0
R
R