R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1876

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 42 User Debugging Interface (H-UDI)
42.4.2
SDINT is a 16-bit register that can be read from or written to by the CPU. Specifying an H-UDI
interrupt command in SDIR via H-UDI pin (Update-IR) sets the INTREQ bit to 1. While an H-
UDI interrupt command is set in SDIR, SDINT which is connected between the TDI and TDO
pins can be read as a 32-bit register. In this case, the upper 16 bits will be 0 and the lower 16 bits
represent the SDINT value.
Only 0 can be written to the INTREQ bit by the CPU. While this bit is set to 1, an interrupt request
will continue to be generated. This bit, therefore, should be cleared by the interrupt handling
routine. It is initialized by TRST or in the Test-Logic-Reset state.
Rev. 2.00 May 22, 2009 Page 1806 of 1982
REJ09B0256-0200
Initial value:
Bit
15 to 1
0
R/W:
Bit:
Interrupt Source Register (SDINT)
Bit Name

INTREQ
15
R
0
14
R
0
13
R
0
Initial
Value
All 0
0
12
R
0
11
R
0
R/W
R
R/W
10
R
0
Description
Reserved
For reading from or writing to this bit, see General
Precautions on Handling of Product.
Interrupt Request
Indicates whether or not an interrupt by an H-UDI
interrupt command has occurred. Clearing this bit to 0
by the CPU cancels an interrupt request. When writing
1 to this bit, the previous value is maintained.
R
9
0
R
8
0
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
INTREQ
R/W
0
0