R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1344

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 30 SIM Card Module (SIM)
1. Follow the initialization procedure above to initialize the smart card interface.
2. Confirm that the ERS bit (error flag) in SCSSR is cleared to 0.
3. Repeat steps (2) and (3) until it can be confirmed that the TDRE flag in SCSSR is set to 1.
4. Write transmit data to SCTDR, and perform transmission. At this time, the TDRE flag is
5. When performing continuous data transmission, return to step (2).
6. When transmission is ended, clear the TE bit to 0.
Interrupt processing can be performed in the above series of processing.
When the TIE bit is set to 1 to enable interrupt requests and if transmission is started and the
TDRE flag is set to 1, a transmit data empty interrupt (TXI) request is issued. When the RIE bit is
set to 1 to enable interrupt requests and if an error occurs during transmission and the ERS flag is
set to 1, a transmit/receive error interrupt (ERI) request is issued.
For details, refer to Interrupt Operations in section 30.4.5, Data Transmit/Receive Operation.
Rev. 2.00 May 22, 2009 Page 1274 of 1982
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automatically cleared to 0. When transmission of the start bit is started, the TEND flag is
automatically cleared to 0, and the TDRE flag is automatically set to 1.