R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 113

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Note on Programming:
2.2.3
Figure 2.4 shows the floating-point register configuration. There are thirty-two 32-bit floating-
point registers, FPR0_BANK0 to FPR15_BANK0, AND FPR0_BANK1 to FPR15_BANK1,
comprising two banks. These registers are referenced as FR0 to FR15, DR0/2/4/6/8/10/12/14,
FV0/4/8/12, XF0 to XF15, XD0/2/4/6/8/10/12/14, or XMTRX. Reference names of each register
are defined depending on the state of the FR bit in FPSCR (see figure 2.4).
1. Floating-point registers, FPRn_BANKj (32 registers)
2. Single-precision floating-point registers, FRi (16 registers)
3. Double-precision floating-point registers or single-precision floating-point registers, DRi (8
4. Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises
5. Single-precision floating-point extended registers, XFi (16 registers)
6. Double-precision floating-point extended registers, XDi (8 registers): An XD register
FPR0_BANK0 to FPR15_BANK0
FPR0_BANK1 to FPR15_BANK1
When FPSCR.FR = 0, FR0 to FR15 are assigned to FPR0_BANK0 to FPR15_BANK0;
when FPSCR.FR = 1, FR0 to FR15 are assigned to FPR0_BANK1 to FPR15_BANK1.
registers): A DR register comprises two FR registers.
DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7},
DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15}
four FR registers.
FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7},
FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15}
When FPSCR.FR = 0, XF0 to XF15 are assigned to FPR0_BANK1 to FPR15_BANK1;
when FPSCR.FR = 1, XF0 to XF15 are assigned to FPR0_BANK0 to FPR15_BANK0.
comprises two XF registers.
XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7},
XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15}
Floating-Point Registers
As the user's R0 to R7 are assigned to R0_BANK0 to R7_BANK0, and
after an exception or interrupt R0 to R7 are assigned to R0_BANK1 to
R7_BANK1, it is not necessary for the interrupt handler to save and
restore the user's R0 to R7 (R0_BANK0 to R7_BANK0).
Rev. 2.00 May 22, 2009 Page 43 of 1982
Section 2 Programming Model
REJ09B0256-0200