R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1584

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 36 USB Function Controller (USBF)
Rev. 2.00 May 22, 2009 Page 1514 of 1982
REJ09B0256-0200
Bit
3
2
Bit Name
EP5 TR
EP5 TS
Initial Value
0
0
R/W Description
R/W EP5 (Isochronous-in) Transmit Request
R/W EP5 (Isochronous-in) Normal Transmission
Flag indicating the FIFO state of EP5.
After the SOF packet is received, the FIFO buffer is
switched automatically. The FIFO buffer which has
transmitted data to the host in the previous frame
(before SOF reception) can be written to by the CPU.
This bit indicates the transmit state in the previous
frame.
[Setting condition]
The FIFO buffer to be transmitted is empty when an IN
token is issued from the host to EP5.
[Clearing conditions]
•
•
Flag indicating the FIFO state of EP5.
After the SOF packet is received, the FIFO buffer is
switched automatically. The FIFO buffer which has
transmitted data to the host in the previous frame
(before SOF reception) can be written to by the CPU.
This bit indicates the transmit state in the previous
frame.
[Setting condition]
When a transmission was carried out normally in the
previous frame.
[Clearing conditions]
•
•
When reset
When 0 is written to by CPU
When reset
When 0 is written to by CPU