R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 979

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.3.71 E-DMAC Receive Request Register (EDRRR)
EDRRR is a 32-bit readable/writable register that issues receive directives to the E-DMAC. After
writing 1 to the RR bit in this register, the E-DMAC reads the receive descriptor at the address
specified by RDLAR. If the RACT bit of this receive descriptor is set to 1 (valid), and the receive
FIFO holds a receive frame, the E-DMAC starts receive DMA transfer. When DMA transfer based
on the first receive descriptor is completed, the E-DMAC reads the next receive descriptor. If the
RACT bit of that receive descriptor is set to 1 (valid), the E-DMAC continues receive DMA
operation. However, if the receive FIFO holds no receive data, the E-DMAC places receive DMA
operation in the standby state. If the RACT bit of the receive descriptor is cleared to 0 (invalid),
the E-DMAC clears the RR bit and stops receive DMAC operation.
Bit
31 to 1
0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name

RR
31
15


R
R
0
0
30
14


R
R
0
0
29
13


R
R
0
0
Initial
Value
All 0
0
28
12


R
R
0
0
27
11


R
R
0
0
R/W
R
R/W
26
10


R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Receive Request
0: Receiving function is disabled*
1: Receive descriptor is read, and the E-DMAC is ready
25

R

R
0
9
0
If 0 is written to this bit, the E-DMAC stops receive
operation after DMA transfer of one frame has
completed and then clears this bit.
The E-DMAC clears this bit when receive descriptor
empty occurs.
to receive
24

R

R
0
8
0
Section 23 Gigabit Ethernet Controller (GETHER)
23


R
R
0
7
0
Rev. 2.00 May 22, 2009 Page 909 of 1982
22


R
R
0
6
0
21


R
R
0
5
0
20

R

R
0
4
0
19


R
R
0
3
0
REJ09B0256-0200
18


R
R
0
2
0
17


R
0
1
0
R/W
RR
16

R
0
0
0