R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1423

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

31.5
31.5.1
To transfer data using the DMAC, set MMCIF (DMACR) after setting the DMAC. Transmit the
read command after setting DMACR.
When using DMA, next block read is resumed automatically when the AUTO bit in DMACR is
set to 1 under the condition that normal read is detected after a block transfer end of a pre-defined
multiblock transfer. Figure 31.19 shows an example of the operational flow for a pre-defined
multiblock read in MMC mode using auto-mode.
• Clear FIFO.
• Set the block number to TBNCR.
• Set DMACR.
• Read command transmission is started.
• Command response and read data are received from card.
• When the card does not return the command response, the command response is detected by
• The end of the command sequence is detected by poling the BUSY flag in CSTR or through
• An error in a command sequence (during data reception) is detected through the CRC error
• The data remains in FIFO after the read sequence end. Set the SET[2:0] bits in DMACR to 100
• Confirm the DMAC transfer completion and clear the DMAEN bit in DMACR to 0.
• Set the CMDOFF bit to 1 and clear DMACR to H'00 when a CRC error (CRCERI) or
• Set the CMDOFF bit to 1, clear DMACR to H'00, and clear FIFO when a CRC error
Note: * In multiblock transfer, when the command sequence is ended (1 is written to the
the command timeout error (CTERI).
the pre-defined multiblock transfer end flag (BTI).
flag or data timeout flag. When these flags are detected, set the CMDOFF bit in OPCR to 1,
issue CMD12, and suspend the command sequence.
to read all data left in FIFO if necessary.
command timeout error (CTERI) occurs in the command response reception.
(CRCERI) or data timeout error (DTERI) occurs in the read data reception.
Operations when Using DMAC
Operation in Read Sequence
CMDOFF bit) before command response reception ends (CRPI), the command
response may not be received correctly. Therefore, to receive the command response,
the command sequence must be continued (set the RD_CONTI bit to 1) until the
command response reception ends.
Access from the DMAC to FIFO must be done in bytes or words.
Section 31 Multimedia Card Interface (MMCIF)
Rev. 2.00 May 22, 2009 Page 1353 of 1982
REJ09B0256-0200