R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1092

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 25 Stream Interface (STIF)
(d) Time Stamp Setting at Reception
For the time stamp setting at strobe reception, only reception with a fixed value added can be
selected. Set the STMP[1:0] bits in STIMDR to 00.
• Reception with a fixed value added
(e)
During strobe reception, the following interrupt sources are available.
• Receive packet count interrupt
• Receive FIFO overflow interrupt
25.4.3
(1)
When starting the stream data transmit processing, set the following DMAC registers.
• Set the external memory address in SAR.
• Set the P4 area address for the data register of the transmit/receive FIFO of the STIF in DAR.
• Set the DMA transfer count in TCR according to the following equation. Only the value
• Set H'0001 0001 in TCRB. The upper bits indicate the transfer count until reloading is
• Set H'0E20 5819 in CHCR.*
• Set the module ID and register ID (H'D3 when STIF channel 0 is used and H'D7 when STIF
Note: * Besides a purpose to use STIF, do not set CHCR.DVMD bit to 1.
Rev. 2.00 May 22, 2009 Page 1022 of 1982
REJ09B0256-0200
The value set in the time stamp counter is used as the fixed value. Counting is not performed.
When the packet length is 188 bytes, a 4-byte fixed value is added to the front of the packet.
When the packet length is 192 bytes, the first four bytes of the packet are overwritten with the
fixed value.
calculated below should be set.
performed, and the lower bits indicate the transfer counter value.
channel 1 is used) of the transfer request source in the DMARS bits corresponding to the used
DMAC channel.
Interrupt Sources during Reception
DMAC Register Setting
Transfer count =
Stream Data Transmit Operation
(192 bytes + work area byte count)/16 bytes × transmit/receive packet count