R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1188

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 27 Serial Communication Interface with FIFO (SCIF)
(4)
The input/output condition and level of the SCIF_TXD pin are determined by bits SPB2IO and
SPB2DT in SCSPTR. This feature can be used to send a break signal.
After the serial transmitter is initialized and until the TE bit is set to 1 (enabling transmission), the
SCIF_TXD pin function is not selected and the value of the SPB2DT bit substitutes for the mark
state. The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high
level) in the beginning.
To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low
level), and then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized, regardless of the current transmission state, and 0 is output from the
SCIF_TXD pin.
(5)
In asynchronous mode, the SCIF operates on a base clock with a frequency of 16 times the bit
rate.
In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the
base clock. Receive data is latched at the rising edge of the eighth base clock pulse.
The timing is shown in figure 27.22.
Rev. 2.00 May 22, 2009 Page 1118 of 1982
REJ09B0256-0200
Base clock
Receive data
(SCIF_RXD)
Synchronization
sampling timing
Data sampling
timing
Sending a Break Signal
Receive Data Sampling Timing and Receive Margin in Asynchronous Mode
Figure 27.22 Receive Data Sampling Timing in Asynchronous Mode
0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5
8 clocks
Start bit
16 clocks
–7.5 clocks
+7.5 clocks
D0
D1