R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 727

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(2)
1. Reset sources
• Input low level via MRESET pin.
• When a general exception other than a user break occurs while the BL bit is set to 1 in SR
• When the WDTCNT overflows while the WT/IT bit and the RSTS bit are set to 1 in WTCSR.
2. Branch destination address: H’A000 0000
3. Operation in branch
Exception code H’020 is set in the EXPEVT register. The VBR and SR registers are initialized,
and the program branches to PC =H’A000 0000. By initialization, the VBR register is set to
H’0000 0000. In the SR register, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0,
and the IMASK3 to IMASK0 bits (interrupt mask level) are set to B’1111.
The CPU and the peripheral modules are also initialized. For details, see the register descriptions
in each section.
17.4.2
1. Set the WDTCNT overflow interval value in WDTST.
2. Set the WT/IT bit in WDTCSR to 1, select the type of reset with the RSTS bit.
3. When the TME bit in WDTCSR is set to 1, the WDT count starts.
Manual reset
Manual_reset()
{
}
Using watchdog timer mode
EXPEVT = H'0000 0020;
VBR = H'0000 0000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(Manual);
PC = H'A000 0000;
Section 17 Watchdog Timer and Reset (WDT)
Rev. 2.00 May 22, 2009 Page 657 of 1982
REJ09B0256-0200

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