R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1028

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
23.4.2
(1)
When 11 is written to the TR bits in EDTRR with the TE bit in ECMR set to 1 and there is empty
space of 32 bytes or more in the transmit FIFO, the E-DMAC reads the descriptor following the
previously used descriptor from the transmit descriptor list (or the descriptor indicated by TDLAR
at the initial startup).
If the TACT bit of the read descriptor is set to 1 (valid), the E-DMAC sequentially reads transmit
frame data from the transmit buffer start address specified by TD2 and transfers the data to the
transmit FIFO. The E-DMAC configures a transmit frame and starts transmission to the
GMII/MII/RMII. After DMA transfer of data equivalent to the buffer length specified in the
descriptor, the following processing is carried out according to the TFP value.
• TFP = 10 (start of a frame)
• TFP = 01 or 11 (end of a frame)
• TFP = 00 (frame continued)
As long as the TACT bit of a read descriptor is set to 1 (valid), the reading of E-DMAC
descriptors and the transmission of frames continue.
When a descriptor with the TACT bit cleared to 0 (invalid) is read, the E-DMAC performs the
following processing and completes transmit processing.
• Clears the TR bits in EDTRR to 00.
• Writes the TC bits in EESR to 11 and generates an interrupt to the CPU.
The E-DMAC can store up to four frames of data in the transmit FIFO.
Rev. 2.00 May 22, 2009 Page 958 of 1982
REJ09B0256-0200
Descriptor write-back (writing 0 to the TACT bit) is performed after completion of DMA
transfer.
Descriptor write-back (writing 0 to the TACT bit and writing status) is performed after
completion of frame transmission.
Descriptor write-back is not performed. The TACT bit retains the value 1.
Transmission Procedure and Processing Flow
Transmission