R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 45

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 13.8 Endian Conversion from SuperHyway Bus to PCI Local bus
Figure 13.9 PCI local bus to SuperHyway bus Memory Map .................................................... 539
Figure 13.10 PCI Local Bus to SuperHyway Bus Address Translation
Figure 13.11 PCI Local Bus to SuperHyway Bus Address Translation (PCIC I/O Space) ........ 542
Figure 13.12 Endian Conversion from PCI Local Bus to SuperHyway bus
Figure 13.13 Endian Conversion from PCI Local Bus to SuperHyway bus
Figure 13.14 Cache Flush/Purge Execution Flow for PCI local Bus to SuperHyway Bus......... 547
Figure 13.15 Address Generation for Type 0 Configuration Access.......................................... 549
Figure 13.16 PCI Local Bus Power Down State Transition ....................................................... 552
Figure 13.17 Master Write Cycle in Host Bus Bridge Mode (Single)........................................ 553
Figure 13.18 Master Read Cycle in Host Bus Bridge Mode (Single)......................................... 554
Figure 13.19 Master Write Cycle in Normal Mode (Burst)........................................................ 555
Figure 13.20 Master Read Cycle in Normal Mode (Burst)......................................................... 556
Figure 13.21 Target Read Cycle in Normal Mode (Single)........................................................ 558
Figure 13.22 Target Write Cycle in Normal Mode (Single)....................................................... 559
Figure 13.23 Target Memory Read Cycle in Host Bus Bridge Mode (Burst) ............................ 560
Figure 13.24 Target Memory Write Cycle in Host Bus Bridge Mode (Burst) ........................... 561
Figure 13.25 Master Write Cycle in Host Bus Bridge Mode (Burst, with stepping) .................. 562
Figure 13.26 Target Memory Read Cycle in Host Bus Bridge Mode (Burst, with stepping)..... 563
Figure 13.27 Timing Example of Device (REQm) Not Executing REQ Negation and
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.1 Block Diagram of DMAC ....................................................................................... 568
Figure 14.2 Round-Robin Mode................................................................................................. 598
Figure 14.3 Changes in Channel Priority in Round-Robin Mode............................................... 599
Figure 14.4 Data Flow of Dual Address Mode........................................................................... 600
Figure 14.5 Example of DMA Transfer Timing in Dual Address Mode
Figure 14.6 DMA Transfer Timing Example in Cycle-Steal Normal Mode 1
Figure 14.7 DMA Transfer Timing Example in Cycle-Steal Normal Mode 2
Figure 14.8 Example of DMA Transfer Timing in Cycle Steal Intermittent Mode
Figure 14.9 DMA Transfer Timing Example in Burst Mode (DREQ Low Level Detection) .... 604
Figure 14.10 Bus State when Multiple Channels are Operating ................................................. 608
(Source: Ordinary Memory, Destination: Ordinary Memory)................................. 601
(DREQ Low Level Detection)................................................................................. 602
(DREQ Low Level Detection)................................................................................. 603
(DREQ Low Level Detection)................................................................................. 603
(Byte Swapping: TBS = 1) ...................................................................................... 538
(Local Address Space 0/1)..................................................................................... 541
(Non-Byte Swapping: TBS = 0) ............................................................................ 544
(Non-Byte Swapping: TBS = 1) ............................................................................ 545
FRAME Assertion Simultaneously ....................................................................... 564
Rev. 2.00 May 22, 2009 Page xliii of lxviii