R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1302

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 29 Serial I/O with FIFO (SIOF)
(2)
Figure 29.10 shows an example of settings and operation for master mode reception.
Rev. 2.00 May 22, 2009 Page 1232 of 1982
REJ09B0256-0200
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Reception in Master Mode
Store SIOFRXD receive data in SIRDR
SIRDAR, SICDAR, and SIFCTR
synchronously with SIOF_SYNC
Clear the RXE bit in SICTR to 0
Set the SCKE bit in SICTR to 1
Set the FSE and RXE bits
Start SIOFSCK output
Set SIMDR, SISCR,
Figure 29.10 Example of Receive Operation in Master Mode
in SICTR to 1
RDREQ = 1?
Read SIRDR
Flow Chart
Transfer
ended?
Start
End
Yes
Yes
No
No
Set operating mode, serial clock,
slot positions for receive data,
slot position for control data, and
FIFO request threshold value
Set operation start for baud rate
generator
Set the start for frame synchronous
signal output and enable
reception
Read receive data
Set to disable reception
SIOF Settings
Output serial clock
Output frame synchronous
signal
Issue receive transfer
request according to the
receive FIFO threshold
value
Reception
End reception
SIOF Operation