R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 348

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Interrupt Controller (INTC)
Rev. 2.00 May 22, 2009 Page 278 of 1982
REJ09B0256-0200
Bit
31 to 26
25
24
23, 22
21
20
19, 18
17
16
15
14, 13
12
11
10
9
8
7
6
5
4
3
Bit Name
—
SCIF2
USBF
—
STIF1
STIF0
—
USBH
GETHER
PCC
—
ADC
TPU
SIM
SIOF2
SIOF1
LCDC
—
IIC1
IIC0
SSI3
Initial
Value
All 1
1
1
All 1
1
1
All 1
1
1
1
All 1
1
1
1
1
1
1
1
1
1
1
R/W
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Function
These bits are always read as 1.
The write value should always
be 1.
Masks SCIF2 interrupts
Masks USBF interrupts
These bits are always read as 1.
The write value should always
be 1.
Masks STIF1 interrupts
Masks STIF0 interrupts
These bits are always read as 1.
The write value should always
be 1.
Masks USBH interrupts
Masks GETHER interrupts
Masks PCC interrupts
These bits are always read as 1.
The write value should always
be 1.
Masks ADC interrupts
Masks TPU interrupts
Masks SIM interrupts
Masks SIOF2 interrupts
Masks SIOF1 interrupts
Masks LCDC interrupts
This bit is always read as 1. The
write value should always be 1.
Masks IIC1 interrupts
Masks IIC0 interrupts
Masks SSI3 interrupts
Description
Masks interrupts for
each peripheral
module.
[When writing]
0: Invalid
1: Interrupts are
[When reading]
0: No mask setting
1: Mask setting
masked