R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 123

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

For the 64-bit data format, see figure 2.5.
2.6
This LSI has major three processing states: the reset state, instruction execution state, and power-
down state.
(1)
In this state the CPU is reset. The reset state is divided into the power-on reset state and the
manual reset.
In the power-on reset state, the internal state of the CPU and the on-chip peripheral module
registers are initialized. In the manual reset state, the internal state of the CPU and some registers
of on-chip peripheral modules are initialized. For details, see register descriptions for each section.
(2)
In this state, the CPU executes program instructions in sequence. The Instruction execution state
has the normal program execution state and the exception handling state.
(3)
In a power-down state, CPU halts operation and power consumption is reduced. The power-down
state is entered by executing a SLEEP instruction. There are two modes in the power-down state:
sleep mode and standby mode.
Reset State
Instruction Execution State
Power-Down State
Processing States
Address A + 4
Address A + 8
Address A
7
31
15
31
Byte 0
A
Word 0
0 7
23
Figure 2.7 Data Formats in Memory
Byte 1 Byte 2 Byte 3
A + 1
Big endian
Longword
0 7
0 15
15
A + 2
Word 1
0 7
7
A + 3
0
0
0
0
7
31
31
15
A + 11
Byte 3
Word 1
0 7
23
A + 10 A + 9
Byte 2 Byte 1 Byte 0
Little endian
Longword
Rev. 2.00 May 22, 2009 Page 53 of 1982
0 7
0
15
15
Word 0
0 7
7
Section 2 Programming Model
A + 8
0
0
0
0
Address A + 8
Address A + 4
Address A
REJ09B0256-0200