R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 434

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 11 Local Bus State Controller (LBSC)
For details, see section 12, DDR-SDRAM Interface (DDRIF).
(5)
For area 4, physical address bits A28 to A26 are 100.
The interfaces that can be set for this area are the SRAM, MPX, burst ROM, byte control SRAM,
DDR-SDRAM and PCI interfaces.
A bus width of 8, 16, or 32 bits is selectable with bits SZ [1:0] in CS4BCR. When the MPX
interface is used, a bus width of 32 bits should be selected through bits SZ[1:0] in CS4BCR. When
the byte control SRAM interface is used, select a bus width of 16 or 32 bits. For details, see
section 11.3.2, Memory Bus Width.
When area 4 is accessed, the CS4 signal is asserted (except for DDR-SDRAM and PCI areas). In
the case where the SRAM interface is set, the RD signal, which can be used as OE, and write
control signals WE0 to WE3 are asserted.
As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS4WCR can be selected.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(When the insert number is 0, the RDY signal is ignored.)
The setup time and hold time (cycle number) of the address and CS4 signals to the read and write
strobe signals can be set within a range of 0 to 7 cycles by CS4WCR. The BS hold cycles can be
set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more.
When the DDR-SDRAM or PCI is used, see section 12, DDR-SDRAM Interface (DDRIF) or
section 13, PCI Controller (PCIC), respectively.
(6)
For area 5, external address bits A28 to A26 are 101.
The interfaces that can be set for this area are the SRAM, MPX, burst ROM, PCMCIA, and DDR-
SDRAM interfaces.
When the SRAM or burst ROM interface is used, a bus width of 8, 16, or 32 bits is selectable with
bits SZ[1:0] in CS5BCR. When the MPX interface is used, a bus width of 32 bits should be
selected through bits SZ[1:0] in CS5BCR. When the PCMCIA interface is used, select a bus width
of 8 or 16 bits with SZ[1:0] in CS5BCR. For details, see section 11.3.2, Memory Bus Width.
While the SRAM interface is used, the CS5 signal is asserted when area 5 is accessed. In addition,
the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted.
Rev. 2.00 May 22, 2009 Page 364 of 1982
REJ09B0256-0200
Area 4
Area 5