R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1289

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
29.4
29.4.1
(1)
The following modes are available as the SIOF clock mode.
• Slave mode: SIOF_SCK, SIOF_SYNC input
• Master mode: SIOF_SCK, SIOF_SYNC output
(2)
In SIOF master mode, the baud rate generator (BRG) is used to generate the serial clock. The baud
rate generator consists of the prescaler that can select 32 types of division ratio from 1 to 1/32 with
the BRPS4 to BRPS0 bits in SISCR and divider that can select the division ratio from 1, 1/2, 1/4,
1/8, 1/16, and 1/32, with the BRDV2 to BRDV0 bits in SISCR. The division ratio of the baud rate
generator ranges from 1 to 1/1024 of the product of the division ratios of the prescaler and the
divider.
When the master clock is not divided by the baud rate generator (the division ratio is 1), set the
MSIMM bit in SISCR to 1 and use the master clock without division as a serial clock.
Figure 29.2 shows connections for supply of the serial clock.
Table 29.5 shows an example of serial clock frequency.
Master/Slave Modes
Baud Rate Generator
Operation
Serial Clocks
SIOF_MCLK
SIOF_SCK
Pck
Master clock
Figure 29.2 Serial Clock Supply
Baud rate generator
Pre-
scalar
Divider
1/1 to 1/1024
Master clock
Rev. 2.00 May 22, 2009 Page 1219 of 1982
Section 29 Serial I/O with FIFO (SIOF)
Timing
control
SCKE
Master
REJ09B0256-0200

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