R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 16

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 SuperHyway Bus Bridge (SBR)...................................................... 313
10.1 Features.............................................................................................................................. 313
10.2 Register Descriptions......................................................................................................... 314
10.3 Operation ........................................................................................................................... 317
Section 11 Local Bus State Controller (LBSC)................................................. 319
11.1 Features.............................................................................................................................. 319
11.2 Input/Output Pins............................................................................................................... 322
11.3 Area Overview................................................................................................................... 324
11.4 Register Descriptions......................................................................................................... 333
11.5 Operation ........................................................................................................................... 357
Section 12 DDR-SDRAM Interface (DDRIF) .................................................. 411
12.1 Features.............................................................................................................................. 411
12.2 Input/Output Pins............................................................................................................... 413
12.3 Data Conversion ................................................................................................................ 414
Rev. 2.00 May 22, 2009 Page xiv of lxviii
10.2.1 Bus Arbitration Priority Level Setting Register (SBRIVCLV) ............................ 315
10.2.2 SuperHyway Bus Priority Control Resister (PRPRICR) ...................................... 316
10.3.1 SuperHyway Bus Interface ................................................................................... 317
10.3.2 Bus Arbitration ..................................................................................................... 317
11.3.1 Space Divisions .................................................................................................... 324
11.3.2 Memory Bus Width .............................................................................................. 328
11.3.3 Data Alignment..................................................................................................... 329
11.3.4 PCMCIA Support ................................................................................................. 329
11.4.1 Memory Address Map Select Register (MMSELR)............................................. 334
11.4.2 Bus Control Register (BCR) ................................................................................. 336
11.4.3 CSn Bus Control Register (CSnBCR) .................................................................. 341
11.4.4 CSn Wait Control Register (CSnWCR)................................................................ 347
11.4.5 CSn PCMCIA Control Register (CSnPCR).......................................................... 352
11.5.1 Endian/Access Size and Data Alignment.............................................................. 357
11.5.2 Areas..................................................................................................................... 362
11.5.3 SRAM interface .................................................................................................... 366
11.5.4 Burst ROM Interface ............................................................................................ 374
11.5.5 PCMCIA Interface................................................................................................ 376
11.5.6 MPX Interface ...................................................................................................... 387
11.5.7 Byte Control SRAM Interface .............................................................................. 400
11.5.8 Wait Cycles between Accesses............................................................................. 404
11.5.9 Bus Arbitration ..................................................................................................... 406
11.5.10 Master Mode......................................................................................................... 408
11.5.11 Cooperation between Master and Slave................................................................ 409