R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 627
R5S77631Y266BGV
Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R5S77631Y266BGV.pdf
(2056 pages)
Specifications of R5S77631Y266BGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 13 PCI Controller (PCIC)
(2)
Target Read/Write Cycle Timing
The PCIC responds to target memory burst read accesses from an external master by retries until 8
longword (32-bit) data are prepared in the PCIC's internal FIFO. That is, it always responds to the
first target burst read with a retry. For a single read access, the PCIC reaponds as soon as the data
is prepared.
Also, when a target memory write access is made, the content of the data is guaranteed until the
write data is completely written to the local memory if reading the target write data immediately
after write access.
Only single transfers are supported in the case of target accesses of the configuration space and
I/O space. If there is a burst access request, the external master is disconnected on completion of
the first transfer. Note that the DEVSEL response speed is fixed at 2 clocks (Medium) in the case
of target access to the PCIC.
Figure 13.21 shows an example target single read cycle in normal mode. Figure 13.22 shows an
example target single write cycle in normal mode. Figure 13.23 is an example of a target burst
read cycle in host bus bridge mode. And figure 13.24 is an example of a target burst write cycle in
host bus bridge mode.
Rev. 2.00 May 22, 2009 Page 557 of 1982
REJ09B0256-0200
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