R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1379
![IC SUPERH MPU ROMLESS 499BGA](/photos/12/43/124352/r5s77631y266bgv_sml.jpg)
R5S77631Y266BGV
Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R5S77631Y266BGV.pdf
(2056 pages)
Specifications of R5S77631Y266BGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 1379 of 2056
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31.3.10 Data Timeout Register (DTOUTR)
DTOUTR specifies the period for generating a data timeout. The 16-bit counter (DTOUTC) and a
prescaler count peripheral clock 1 to monitor the data timeout. The prescaler always counts
peripheral clock 1, and outputs a count pulse at every 10,000 peripheral clock 1 cycles. The initial
value of DTOUTC is 0, and DTOUTC starts counting the prescaler output at the start of the
command sequence. DTOUTC is cleared when the command sequence has ended, or when the
command sequence has been aborted by setting the CMDOFF bit to 1, after which the DTOUTC
stops counting the prescaler output.
When the command sequence does not end, DTOUTC continues counting the prescaler output,
and enters the data timeout error states when the number of prescaler outputs reaches the number
specified in DTOUTR. When the DTERIE bit in INTCR1 is set to 1, the DTERI flag in INTSTR1
is set. To perform data timeout error handling, abort the command sequence by setting the
CMDOFF bit to 1, and then clear the DTERI flag.
For a command with data busy status, data timeout cannot be monitored since the command
sequence is terminated before entering the data busy state. Timeout in the data busy state should
be monitored by firmware. Setting DTOUTR to 0 will cause a timeout immediately after the start
of the command sequence.
Bit
15 to 0
Initial value:
R/W:
Bit:
Bit Name
DTOUTR
R/W
15
1
R/W
14
1
R/W
13
1
Initial
Value
All 1
R/W
12
1
R/W
11
R/W
R/W
1
R/W
10
1
Description
Data Timeout Time/10,000
Data timeout time: Peripheral clock 1 cycle × DTOUTR
setting value × 10,000.
R/W
9
1
R/W
DTOUTR
8
1
R/W
Section 31 Multimedia Card Interface (MMCIF)
7
1
Rev. 2.00 May 22, 2009 Page 1309 of 1982
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
REJ09B0256-0200
R/W
2
1
R/W
1
1
R/W
0
1
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