R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1349

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 30 SIM Card Module (SIM)
generated, and the RIE bit should be set to 1 so that an ERI request is issued. The ERS flag set
when an error signal is received is not cleared automatically, and so should be cleared by sending
an interrupt request to the CPU.
In receive operation, when the RDRF flag in SCSSR is set to 1, a DMA transfer request for
receive data full is issued. By setting a DMA transfer request for receive data full in advance as a
DMAC activation source, the DMAC can be activated and made to transfer data when a DMA
transfer request for receive data full occurs.
When in T = 0 mode and if a parity error occurs during reception, a data retransmit request is
issued. At this time the RDRF flag is not set, and a DMA transfer request is not issued, so the
number of bytes specified to the DMAC can be received.
When using the DMAC for receive data processing and performing error processing as a result of
an interrupt request sent to the CPU, the RIE bit should be set to 1 and the EIO bit to 1, so that no
RXI requests are generated and only ERI requests are generated.
The PER, ORER, and WAIT_ER flags that are set by a receive error are not automatically cleared,
and so should be cleared by sending an interrupt request to the CPU.
When using the DMAC for transmission and reception, the DMAC should always be set first and
put into the enabled state, before setting the smart card interface.
Rev. 2.00 May 22, 2009 Page 1279 of 1982
REJ09B0256-0200

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