R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 377

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.5.2
When handling multiple interrupts, an interrupt handling routine should include the following
procedures:
1. To identify the interrupt source, branch to a specific interrupt handling routine for the interrupt
2. Clear the interrupt source in each specific interrupt handling routine.
3. Save SSR and SPC to the stack.
4. Clear the BL bit in SR. When the INTMU bit in CPUOPM is set to 1, the interrupt mask level
5. Handle the interrupt as required.
6. Set the BL bit in SR to 1.
7. Restore SSR and SPC from memory.
8. Execute the RTE instruction.
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted if multiple interrupts occur after step 4. This reduces the interrupt
response time for urgent processing.
9.5.3
Setting the MAI bit in ICR0 to 1 masks interrupts while the NMI signal is low regardless of the
BL and IMASK bit settings in SR.
• Normal operation or sleep mode
All interrupts are masked while the NMI signal is low. Note that only NMI interrupts due to NMI
signal input occur.
source by using the INTEVT code as an offset.
(IMASK) in SR is automatically modified to the level of the accepted interrupt. When the
INTMU bit in CPUOPM is cleared to 0, set the IMASK bit in SR by software to the accepted
interrupt level.
Multiple Interrupts
Interrupt Masking by MAI Bit
Rev. 2.00 May 22, 2009 Page 307 of 1982
Section 9 Interrupt Controller (INTC)
REJ09B0256-0200