R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 858

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
Rev. 2.00 May 22, 2009 Page 788 of 1982
REJ09B0256-0200
Name
RMII
management
data clock
RMII
management
data I/O
RMII
management
data clock
(mirror 0 pin)
RMII
management
data I/O (mirror
0 pin)
RMII
management
data clock
(mirror 1 pin)
RMII
management
data I/O (mirror
1 pin)
Link status
Wake-On-LAN
PHY interrupt
GMII transmit
clock
RMII carrier
detection
RMII receive
error
RMII receive
data
RMII receive
data
RMII transmit
enable
0
Port
Abbreviation
RMII0_MDC
RMII0_MDIO
RMII0M0_MDC
RMII0M0_MDIO
RMII0M1_MDC
RMII0M1_MDIO
ET0_LINKSTA
ET0_WOL
ET0_PHY-INT
GET0_GTX-CLK Output
RMII0_CRS_DV
RMII0_RX_ER
RMII0_RXD0
RMII0_RXD1
RMII0_TXD_EN
Output
I/O
Output
I/O
Output
I/O
Output
Input
Input
Input
Input
Input
Output
I/O
Input
Function
Reference clock signal for information
transfer via RMII0_MDIO in RMII mode
Bidirectional signal for exchange of
management information between STA
and PHY in RMII mode
Reference clock signal for information
transfer via RMII0M0_MDIO in RMII
mode (mirror 0 pin)
Bidirectional signal for exchange of
management information between STA
and PHY in RMII mode (mirror 0 pin)
Reference clock signal for information
transfer via RMII0M1_MDIO in RMII
mode (mirror 1 pin)
Bidirectional signal for exchange of
management information between STA
and PHY in RMII mode (mirror 1 pin)
Inputs link status from PHY-LSI
Signal indicating reception of Magic
Packet
Interrupt signal from PHY
Transmit signal timing reference signal in
GMII mode
Carrier detection signal in RMII mode
Identifies error state occurred during data
reception in RMII mode
2-bit receive data in RMII mode
2-bit receive data in RMII mode
Indicates that transmit data is ready on
RMII0_TXD0 and RMII0_TXD1 in RMII
mode