R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1859

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

41.3.5
1. Sequential break conditions can be specified by setting the MFE and MFI bits in the match
2. For channel 1, the execution count break condition can also be included in the sequential break
3. If the match conditions for the first and second channels in the sequence are satisfied within a
• When the Match Condition is Satisfied at the Instruction Fetch Cycle for Both the First and
• When the match condition is satisfied at the instruction fetch cycle for the first channel in the
Instruction B is 0 instruction after instruction A
Instruction B is one instruction after instruction A Sequential operation is not guaranteed.
Instruction B is two or more instructions after
instruction A
Instruction B is 0 or one instruction after
instruction A
Instruction B is two or more instructions after
instruction A
condition setting registers (CBR0 and CBR1). (Sequential break involves two cases such that
channel 0 break condition is satisfied then channel 1 break condition is satisfied, and vice
versa.) To use the sequential break function, clear the MFE bit of the match condition setting
register and the BIE bit of the match operation setting register of the first channel in the
sequence, and set the MFE bit and specify the number of the second channel in the sequence
using the MFI bit in the match condition setting register of the second channel in the sequence.
If the sequential break condition is set, the condition match flag is set every time the match
condition is satisfied for each channel. When the condition has been satisfied for the first
channel in the sequence but not for the second channel in the sequence, clear the condition
match flag for the first channel in the sequence in order to release the first channel in the
sequence from the match state.
conditions.
significantly short time, sequential operation may not be guaranteed in some cases, as shown
below.
Second Channels in the Sequence:
sequence whereas the match condition is satisfied at the operand access cycle for the second
channel in the sequence:
Sequential Break
Equivalent to setting the same addresses; do
not use this setting.
Sequential operation is guaranteed.
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
Rev. 2.00 May 22, 2009 Page 1789 of 1982
Section 41 User Break Controller (UBC)
REJ09B0256-0200