R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1603

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

36.3.22 EP4 Data Register (EPDR4)
EPDR4 is a 128-byte receive FIFO buffer for endpoint 4. EPDR4 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. The number of receive byte is displayed in
the EP4 receive data size register. The receive data is fixed when an SOF packet is received.
Accordingly, all receive data must be read until the next SOF packet is received. When the next
SOF packet is received, the FIFO side is automatically switched over, and the previous data will
not be possible to be read. This FIFO buffer can be initialized by means of EP4CLR in the FCLR1
register.
Bit
31 to 8 
7 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit: 31
Bit: 15
Bit Name
D[7:0]
—
—
—
—
R
R
30
14
—
—
—
—
R
R
29
13
—
—
—
—
R
R
Initial Value R/W Description
Undefined
Undefined
28
—
12
—
—
—
R
R
27
11
—
—
—
—
R
R
26
—
10
—
—
—
R
R
R
R
25
—
—
—
—
R
R
9
Data register for endpoint 4 transfer
Reserved
These bits are always read as undefined value.
24
—
—
—
—
R
R
8
23
—
—
—
R
R
7
Section 36 USB Function Controller (USBF)
Rev. 2.00 May 22, 2009 Page 1533 of 1982
22
—
—
—
R
R
6
21
—
—
—
R
R
5
20
—
—
—
R
R
4
D[7:0]
19
—
—
—
R
R
3
REJ09B0256-0200
18
—
—
—
R
R
2
17
—
—
—
R
R
1
16
—
—
—
R
R
0