R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 256

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Memory Management Unit (MMU)
6.8
When using an LDTLB instruction instead of software to a value to the MMUCR. URC,
execute 1 or 2 below.
1. In 29-bit address mode, follow A. and B. below. In 32-bit address mode, follow A. through B.
2. If a TLB miss exception occurs, add 1 to MMUCR.URC before executing an LDTLB
Notes: 1. An exception handling routine is an entire set of instructions that are executed from the
Rev. 2.00 May 22, 2009 Page 186 of 1982
REJ09B0256-0200
below.
A. Place the TLB miss exception handling routine*
B. Use only one page of the PMB for instruction accesses*
C. In 32-bit address mode, obey 1 and 2 below when recording information in the UTLB in
D. Do not make an attempt to execute the FDIV or FSQRT instruction in the MMU-related
instruction.
instruction accesses*
the P1 or P2 area.
handling routine*
of the PMB.
the MMU-related exception*
a. If a TLB miss exception occurs, do not record the page, in which the exception has
b. Exclude the pages for which software has once set 1 to the dirty bit upon occurrence of
exception handling routine.
2. MMU-related exceptions are: instruction TLB miss exception, instruction TLB miss
3. Instruction accesses include the PREFI and ICBI instructions.
Usage Notes
occurred, in the UTLB using the following two operations.
- Specifies the protection key data that causes a protection violation exception upon re-
- Specifies the protection key data that does not cause a protection violation exception
an initial page write exception and intentionally deleted from the TLB or set 0 to the
dirty bit.
address (VBR + offset) upon occurrence of an exception to the RTE for returning to the
original program or to the RTE delay slot.
protection violation exception, data TLB miss exception, data TLB protection violation
exception, and initial page write exception.
execution of the instruction that has caused the TLB miss exception and records the
page, in which the TLB miss exception has occurred, in the UTLB.
in the protection violation exception handling routine to record the page in the UTLB
and re-executes the instruction that has caused the protection violation exception.
1
. In 32-bit address mode, do not place them in the last 64 bytes of a page
3
in the TLB miss exception handling routine should occur solely in
2
handling routine.
1
only in the P1 or P2 area so that all the
3
in the TLB miss exception