R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 502

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 DDR-SDRAM Interface (DDRIF)
12.5
12.5.1
The DDR-SDRAM is accessed with a burst length of 2. Read or write commands that hit the page
are issued continuously and read data continuously.
12.5.2
Since the internal state of the DDR-SDRAM is undefined immediately after a power-on, initialize
the SDRAM according to the following sequence. Otherwise the device may be damaged.
An example of the initialization sequence for the DDR-SDRAM is shown below. For details, see
each memory manufacturer's datasheet.
1. Turn on the four power supplies to the DDR-SDRAM in the following order: VDD, VDDQ,
2. After the power supply, reference voltage, and clock are stabilized, maintain the current state
3. Perform a dummy read to any DDR-SDRAM address.
4. Set MIM to enable the DDR-SDRAM controller, set the endian mode, and so on.
5. Set SDR and STR.
6. Use the SMS field in SCR to enable the CKE pin.
7. Use the SMS field in SCR to issue the all-bank precharge (PREALL) command.
8. Use SDMR to issue the EMRS command and enable the DLL.
Rev. 2.00 May 22, 2009 Page 432 of 1982
REJ09B0256-0200
VREF, and VTT.
for at least 200 µs.
Operation
DDR-SDRAM Access
DDR-SDRAM Initialization Sequence
ACT
ACT
Write data
Figure 12.4 DDR-SDRAM Access
Write command
read command
read data
WR
RD
WR
RD
D
D
WR
RD
D
D
D
WR
RD
D
D
D
D
D
D
D
D
D
D
D