R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 939

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
23.3.44 Added Qtag Value Set Register (Port 0 to 1) (TSU_ADQT0)
TSU_ADQT0 sets the Qtag data to be added in the conversion of normal Ethernet frames (no
Qtag) to IEEE802.1Q frames (with Qtag) in port 0 to 1 relay operations (if bits QTAG0[2:0] in
TSU_QTAG0 are set to H'3 or H'7 when using the Qtag adding function). This register must not
be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0
or the FWEN1 bit in TSU_FWEN1 is set to 1).
Bit
31 to 16
15 to 13
12
11 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
QTAG0[31:16] H'8100 R/W Be sure to set the value of the upper 16 bits
QTAG0[15:13] H'0
QTAG0[11:0]
R/W
R/W
31
15
1
0
QTAG0[15:13]
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
0
H'000
R/W
28
12
R
0
0
R/W
R/W
27
11
0
0
R/W Description
R/W Priority Setting (PRT)
R
R/W V-LAN ID Setting (VID)
R/W
R/W
26
10
0
0
(QTAG0[31:16]) as H'8100 (indicates the Qtag
extension frame format is used). The value read is
H'8100.
These bits set the processing priority of frames with
Qtag. For details on the settings, refer to the
specifications on Qtag control specified in IEEE802.1Q.
Reserved
This bit is always read as 0. The write value should
always be 0.
These bits should be set when frames with Qtag are to
be used in systems supporting V-LAN. For details on
settings, refer to the specifications on Qtag control
specified in IEEE802.1Q.
R/W
R/W
25
0
9
0
QTAG0[31:16]
R/W
R/W
24
1
8
0
Section 23 Gigabit Ethernet Controller (GETHER)
R/W
R/W
23
0
7
0
QTAG0[11:0]
Rev. 2.00 May 22, 2009 Page 869 of 1982
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
REJ09B0256-0200
R/W
R/W
18
0
2
0
R/W
17
0
1
0
R/W
R/W
16
0
0
0

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