R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1327

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
3
Bit Name
PER
Initial
Value
0
R/W
R/W
Description
Parity Error
Indicates that a parity error has occurred during reception,
resulting in abnormal termination.
0: Indicates that reception is in progress, or that reception
[Clearing conditions]
•
•
1: Indicates that a parity error occurred during reception*
[Setting condition]
When the sum of 1 bits in the received data and parity bit
does not match the even or odd parity specified by the O/E
bit in the serial mode register (SCSMR).
Notes:
was completed normally*
On reset
When 0 is written to the PER bit
1. When the RE bit in SCSCR is cleared to 0, the
2. In T = 0 mode, the data received when a parity
PER flag is unaffected, and the previous state
is retained.
error occurs is not transferred to SCRDR, and
the RDRF flag is not set.
On the other hand, in T = 1 mode, the data
received when a parity error occurs is
transferred to SCRDR, and the RDRF flag is
set.
When a parity error occurs, the PER flag
should be cleared to 0 before the sampling
timing for the next parity bit.
Rev. 2.00 May 22, 2009 Page 1257 of 1982
Section 30 SIM Card Module (SIM)
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REJ09B0256-0200
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