R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1725

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
37.6
37.6.1
Follow the procedure below to halt access to VRAM for storing display data (DDR-SDRAM in
area 3).
Procedure for Halting Access to Display Data Storage VRAM:
1. Confirm that the LPS1 and LPS0 bits in LDPMMR are currently set to 1.
2. Clear the DON bit in LDCNTR to 0 (display-off mode).
3. Confirm that the LPS1 and LPS0 bits in LDPMMR have changed to 0.
4. Wait for the display time for a single frame to elapse.
This halting procedure is required before selecting self-refreshing for the display data storage
VRAM (DDR-SDRAM in area 3) or making a transition to standby mode or module standby
mode.
37.6.2
If the NMIFL bit in the NMIFCR register is set to 1 by an NMI interrupt while the LCDC is used,
the LCDC cannot access the VRAM that is used for the display data storage (DDR_SDRAM in
area 3).
As the LCDC continues to output data stored in the lime buffer to the LCD panel data pin, the
LCD display will be stopped if the line buffer becomes empty. Accordingly, NMI interrupts
should be disabled and he NMIFL bit should be cleared to 0 before the line buffer becomes empty.
Usage Notes
Procedure for Halting Access to Display Data Storage VRAM (DDR-SDRAM in
Area 3)
Notes on Using NMI Interrupt
Rev. 2.00 May 22, 2009 Page 1655 of 1982
Section 37 LCD Controller (LCDC)
REJ09B0256-0200

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